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fedl7731-02-04 1 semiconductor this version: jan. 2000 previous version: jan. 2000 MSM7731-02 dual echo canceler & noise canceler with dual codec for hands-free 1/53 general description the msm7731 is an ic device developed for portable, handsfree communication with built-in line echo canceler, acoustic echo canceler, and transmission signal noise canceler. built-in to the voice signal interface is a linear codec for the analog interface on the acoustic-side, and a linear codec for the analog interface on the line-side. on the line-side, in addition to the analog interface, there is also a -law pcm/16-bit linear digital interface. equipped with gain and mute controls for data transmission and reception, a -law pcm/16-bit linear digital interface for memo recording and message output, and transfer clock and sync clock generators for digital communication, this device is ideally suited for a handsfree system. features single 3 v power supply operation (2.7 to 3.6 v) built-in 2-channel (line and acoustic) echo canceler echo attenuation : 35 db (typ.) for white noise cancelable echo delay time : line echo canceler + acoustic echo canceler : tlined = 27 ms (max.) tacoud = 59 ms ? tlined (max.) acoustic echo canceler only : tacoud = 59 ms (max.) built-in transmission signal noise canceler noise attenuation : 17 db (typ.) for white noise 40 db (typ.) for single tone built-in 2-channel codec synchronous transmission and reception enables full duplex operation built-in analog input gain amp stage (max. gain = 30 db) analog output configuration : push-pull drive (can drive a 1.2 k ? load ) built-in transmit slope filter digital interface coding formats : -law pcm, 16-bit linear (2's complement) digital interface sync formats : normal-sync, short-frame-sync built-in digital transmission clock generators sync clock (sync) : 8 khz output transmission clock (bclk) : 64 khz output (-law pcm)/128 khz output (16-bit linear) digital transmission rate external input : 64 to 2048 kbps internal generation : 64 kbps (-law pcm)/128 kbps (16-bit linear) fixed digital interface sync clock (sync) enables automatic power-down master clock frequency : 19.2 mhz compatible with crystal oscillator and crystal low power consumption operating mode : typ. 35 ma (when v dd = 3.0 v in a silent mode) power down operation : typ. 0.02 ma (when v dd = 3.0 v in a silent mode) control by both the serial microcomputer interface and parallel port is possible transmit/receive mute function, transmit/receive programmable gain setting package : 64-pin plastic qfp (qfp64-p-1414-0.80-bk)(product name: MSM7731-02ga)
fedl7731-02-04 1 semiconductor MSM7731-02 2/53 block diagram ain agsx avfro apwi aout sg linear codec (acoustic side) bpf adc rc lpf rc lpf dac lpf vref clock gen timing gen aec controller p/s &s/p ec/nc/sf/pad controller mcu interface lec controller p/s &s/p ? + ? + 1.2 k ? lpada gpada gpadnc rpad gpadl lpadnc tpad attsa center chip power calc . howling detector double talk det acoustic adaptive fir filter ( aaff ) routa rina gaina attra sina souta slope filter noise canleler attrl gainl power calc . howling detector double talk det line adaptive fir filter ( laff ) center chip rinl routl sinl soutl attsl ? + ? + ? + lpadl lpwi dac rc lpf rc lpf adc bpf 1.2 k ? acoustic echo canceler line echo canceler linear codec (line side) lout lvfro lgsx lin lineen agnd avdd dgnd1,2 dvdd1,2 test1-4 test9 pcmo pcmi lthr lgc latt lhd d en exck din dout mcusel ncpad1,2 ncsel1,2 rpad1-4 tpad1-4 ecsel glpadthr slpthr rst pcmeo pcmei athr agc aatt ahd sync syncsel bclk clksel pcmsel p dn / rst mck/x1 x2 lpf + -
fedl7731-02-04 1 semiconductor MSM7731-02 3/53 pin configuration (top view) 64-pin plastic qfp exck din ncsel1 slpthr test1 test2 test3 test4 ncsel2 pdn/rst rst sync bclk clksel pcmi pcmei pcmeo pcmo pcmsel syncsel dout den dvdd2 glpadthr test9 lineen agnd lout lpwi lvfro lgsx lin 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rpad2 rpad1 dgnd2 tpad4 tpad3 tpad2 tpad1 mck/x1 x2 avdd ags x ain avfro apwi aou t sg ecsel mcusel ahd ncpad2 aatt agc dgnd1 athr lhd ncpad1 latt lgc lthr rpad4 dvdd1 rpad3
fedl7731-02-04 1 semiconductor MSM7731-02 4/53 pin functional description ain, agsx these are the acoustic analog input and level adjusting pins. the ain pin is connected to the inverting input of the internal amp and the agsx pin is connected to the amp output. for level adjustment, refer to the diagram below (figure 1). at power-down reset, the agsx pin goes to a high impedance state. avfro, aout, apwi these are acoustic analog output and level adjusting pins. the avfro pin is an audio output and can directly drive 20 k ? . the aout pin is an analog output and can directly drive a load of 1.2 k ? . for level adjustment, refer to the diagram below (figure 1). at power-down reset, these output pins go to a high impedance state. lin, lgsx these are the line analog input and level adjusting pins. the lin pin is connected to the inverting input of the internal amp and the lgsx pin is connected to the amp output. for level adjustment, refer to the diagram below (figure 1). at power-down reset, the lgsx pin goes to a high impedance state. if lin is not used, short the lin and lgsx together. lvfro, lout, lpwi these are acoustic analog output and level adjusting pins. the lvfro pin is an audio output and can directly drive 20 k ? . the lout pin is an analog output and can directly drive a load of 1.2 k ? . for level adjustment, refer to the diagram below (figure 1). at power-down reset, these output pins go to a high impedance state. if lout is not used, short the lpwi and lout pins together. lineen lineen lineen lineen this is the power-down control pin for the line codec. a logic ?0? continues normal operation and a logic ?1? power down only the line codec. if the line codec is not used, power down the line codec and short the lin pin to the lgsx pin and the lpwi pin to the lout pin. this procedure results in the low consumption of electrical power. at power-down, the output pins go to a high impedance state. if the pin setting is changed, reset must be activated by either the pdn / rst pin or the pdn/rst bit (cr0-b7). this pin is ored with cr0-b5 of the control register. refer to the section ?relationship between pins and control registers?. figure 1 analog interface acoustic codec c1 + r1 mic 0.1 f 10 f ? r2 r3 r4 line codec v agsx /vi = r2/r1 30 v agsx = 1.3 v pp r2 20 k ? v o /v avfro = r4/r3 2 v o = 2.6 v pp , v avfro = 1.3 v pp r3 , r4 20 k ? c2 sp spamp vo vi agsx ain sg avfro apwi aout to encoder lgsx lin lvfro lpwi lout vref lineen receive signal transmit signal line side (hand set) acoustic side (mic, speaker) same as acoustic analog interface ? ? + +
fedl7731-02-04 1 semiconductor MSM7731-02 5/53 agnd this is analog ground pin. dgnd1, dgnd2 these are the digital ground pins. av dd this is the analog +3 v power supply pin. dv dd1 , dv dd2 these are the digital +3 v power supply pins. sg this is the output pin for the analog signal ground potential. the output voltage is approximately 1.4 v. insert 10 f and 0.1 f ceramic bypass capacitors between the agnd and sg pin. at power-down rest, this output becomes 0 v. pdn pdn pdn pdn / rst rst rst rst this is the power-down reset control input pin. if a logic ?0? is input to this pin, the device enters the power-down state. at this time, all control register bits, internal variables, and coefficients of echo cancelers and noise cancelers will be reset. after the power-down reset state is released, the device enters the initial mode (refer to the cr0 control register description). during normal operation, set this pin to a logic ?1?. the pdn / rst pin is ored (negative logic) with cr0-b7 of the control register. refer to the section ?relationship between pins and control registers?. mck/x1 this is the master clock input pin. the clock frequency is 19.2 mhz. the input clock may be asynchronous with respect to the sync signal or the bclk signal. refer to figure 2 (a) for an example application of an external clock and figure 2 (b) for an example oscillator circuit. x2 this is the crystal oscillator output pin. if an existing external clock is to be used, leave this pin open and input the clock to the mck pin. refer to figure 2 (b) for an example oscillator circuit. x?tal (19.2 mhz) c r hc-49/u 10 pf 1 m ? cx-91f t.b.d t.b.d figure 2 (a) external clock figure2 (b) oscillator circuit application example example mck/x1 x2 c mck/x1 x2 c x?tal r
fedl7731-02-04 1 semiconductor MSM7731-02 6/53 sync this is the 8 khz sync signal i/o pin for digital data communication. this pin is switched to unction as an input or output by the clksel pin. if the internal clock mode is selected by the clksel pin, an 8 khz clock synchronized to be bclk signal is output and digital data communication is performed. if the external clock mode is selected by the clksel pin, this pin becomes an input that requires an 8 khz clock input synchronized to be bclk pin, and digital data communication is performed based on this input clock. this pin enables automatic power-down control. fixing this pin to a logic ?1? or logic ?0? causes this device to enter the power-down state. two kinds of power-down modes can be selected by the sypdn (cr11-b0) bit of the control register. for the power-down mode, refer to the description of control register cr11. bclk this is the shift clock i/o pin for digital data communication. this pin is switched to function as an input or output by the clksel pin. if the internal clock mode is selected by the clksel pin, a 64 khz or 128 khz clock synchronized to the sync signal is output and digital data communication is performed. switching between 64 khz and 128 khz is performed by the pcmsel pin or pcmsel (cr11-b1) bit. if -law pcm is selected by the pcmsel pin or pcmsel bit, a 64 khz clock is output. or, if 16-bit linear mode is selected, a 128 khz clock is output. if the external clock mode is selected by the clksel pin, this pin becomes an input that requires a clock input synchronized to the sync. in this case, the clock frequency range is from 64 khz to 2048 khz. clksel this pin selects internal or external clock modes for the sync and bclk signals. a logic ?0? selects the internal clock mode. at this time, sync and bclk pins are configured as output pins and each internally generated clock is output to perform digital data communication. a logic ?1? selects the external clock mode and configures the sync and bclk pins as input pins. at this time, digital data communication is performed with the externally input sync and bclk clocks. if digital data communication is not used, set this pin to a logic ?0? to select internal clocks. if the pin setting is changed, reset must be activated by either the pdn / rst pin or the pdn/rst bit (cr0-b7). pcmi this is the digital receive signal input pin on the line-side. this input signal is shifted at the rising edge of the bclk signal and input. the beginning of digital data is identified on the rising edge of the sync signal. the coding format can be selected as -law pcm or 16-bit linear (2?s complement) by the pcmsel pin or pcmsel (cr11-b1) bit. if the pcmi pin is not used, set it to a logic ?1? if -law pcm has been selected, or a logic ?0? if 16-bit linear mode has been selected. the sync format can be selected as normal-sync or short-frame-sync by the syncsel pin. refer to figure 3 for the timing. this digital input signal is added internally to the codec digital output signal. be careful of overflow when using the codec. pcmo this is the digital transmit signal output pin on the line-side. this output signal is synchronized to the rising edge of the bclk and sync signals and then output. when not used for output, this pin is in the high impedance state. it is at high impedance during the power-down reset and the initial modes. the coding format can be selected as -law pcm or 16-bit linear (2?s complement) by the pcmsel pin or pcmsel (cr11-b1) bit. the sync format can be selected as normal-sync or short-frame-sync by the syncsel pin. refer to figure 3 for the timing.
fedl7731-02-04 1 semiconductor MSM7731-02 7/53 pcmei this is the massage signal input pin. use this pin when a massage is output to the speaker on the acoustic-side. this input signal is shifted at the rising edge of the bclk signal and then input. the beginning of digital data is identified on the rising edge of the sync signal. the coding format can be selected as -law pcm or 16-bit linear (2?s complement) by the pcmsel pin or pcmsel (cr11-b1) bit. if the pcmei pin is not used, set it to a logic ?1? if -law pcm has been selected, or a logic ?0? if 16-bit linear mode has been selected. the sync format can be selected as normal-sync or short-frame sync by the syncsel pin. timing is the same as for the pcmi pin (refer to figure 3). this digital input signal is added internally to the echo canceler output signal. be careful of overflow during telephone conversations. pcmeo this output pin is for memo recording. use it with the memo function. this output signal is synchronized to the rising edge of the bclk an sync signals and then output. when not used for output, this pin is in the high impedance state. it is also at high impedance during the power-down reset and the initial modes. the coding format can be selected as -law pcm or 16-bit linear (2?s complement) by the pcmsel pin or pcmsel (cr11-b1) bit. the sync format can be selected as normal-sync or short-frame-sync by the syncsel pin. timing is the same as for the pcmo pin (refer to figure 3). syncsel this is the sync timing selection pin for digital data communication. a logic ?0? selects normal-sync timing and a logic ?1? selects short-frame-sync timing. refer figure 3 for the timing. if the pin setting is changed, reset must be activated by either the pdn / rst pin or the pdn/rst bit (cr0-b7) pcmsel this is the coding format selection pin for digital data communication. a logic ?1? selects -law pcm and a logic ?0? selects 16-bit linear (2?s complement) coding format. when an internal clock is selected, the bclk signal determines the output clock frequency. if the digital interface is not used, set this pin to logic ?0? to select 16-bit linear coding format. if the pin setting is changed, reset must be performed by either the pdn / rst pin or the pdn/rst bit (cr0-b7). this pin is logically ored with the pcmsel bit (cr11-b1). refer to the section ?relationship between pins and control registers?. slpthr this is the ?through mode? control pin for the transmit slope filter. in the ?through mode?, the filter is halted and data is directly output. a logic ?0? selects the normal mode (slope filter operation) and a logic ?1? selects the ?through mode?. the slope filter decreases noises of low frequencies and improves speech quality. refer to the slope filter frequency characteristics. because data is shifted into this pin in synchronization with the rising edge of the sync signal, hold the data at the pin for 250 s or longer. for further details, refer to the electrical characteristics. this pin is ored with the cr1-b1 bit of the control register. refer to the section ?relationship between pins and control registers?.
fedl7731-02-04 1 semiconductor MSM7731-02 8/53 figure 3 digital interface timing sync (b) -law pcm coding format timing (normal sync) bclk pcmi pcmei pcmo pcmeo d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 hi-z d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 sync (a) 16-bit linear coding format timing (normal sync) bclk pcmi pcmei pcmo pcmeo d15 d14 d13 d12 d2 d1 d0 d15 d14 hi-z d15 d14 d13 d12 d2 d1 d0 d15 d14 sync (c) 16-bit linear coding format timing (short-frame sync) bclk pcmi pcmei pcmo pcmeo d15 d14 d13 d2 d1 d0 d15 d3 hi-z d15 d14 d13 d2 d1 d0 d15 hi-z d3 sync (d) -law pcm coding format timing (short-frame sync) bclk pcmi pcmei pcmo pcmeo d7 d7 d6 d5 d4 d3 d2 d1 d0 hi-z d7 d7 d6 d5 d4 d3 d2 d1 d0 hi-z
fedl7731-02-04 1 semiconductor MSM7731-02 9/53 ecsel this is the echo canceler mode selection pin. a logic ?1? selects the single echo canceler mode and a logic ?0? selects the dual echo canceler mode. if the pin setting is changed, reset must be activated by either the pdn / rst pin or the pdn/rst bit (cr0-b7). if the single echo canceler mode is selected, echo canceler control on the line-side is unnecessary. this pin is ored with the cr0-b0 bit of the control register. refer to the section ?relationship between pins and control registers?. lthr/athr this is the ?through mode? control pin for the echo canceler. in the ?through mode?, sinl/a and rinl/a data is directly output to soutl/a and routl/a respectively while each respective echo coefficient is maintained. a logic ?0? selects the normal mode (echo canceler operation) and a logic ?1? selects the ?through mode?. in the through mode, the functions of hd, hld, att and gc are invalid. because data is shifted into this pin in synchronization with the rising edge of the sync signal, hold the data at the pin for 250 s or longer. this pin is ored with the cr4-b7 and cr5-b7 bits of the control register. refer to the section ?relationship between pins and control registers?. lhd lhd lhd lhd / ahd ahd ahd ahd this pin turns on or off the function to detect and cancel the howling that occurs in an acoustic system such as a handsfree communication system. a logic ?0? turns the function on and a logic ?1? turns the function off. this function is valid when the lthr/athr pin is in the normal mode. because data is shifted into this pin in synchronization with the rising edge of the sync signal, hold the data at the pin for 250 s or longer. this pin is ored with the cr4-b4 and cr4-b4 and cr5-b4 bits of the control register. refer to the section ?relationship between pins and control registers?. latt latt latt latt this pin turns on or off the att function to prevent howling by means of attenuators (attsl, attrl) provided in the rinl inputs and soutl outputs of the echo canceler. a logic ?0? turns on and a logic ?1? turns off the att function. if input is only to rinl, the attsl for soutl is activated. if input is only to sinl, or if there is input to both sinl and rinl, the attrl for rinl input is activated. the att value of each attenuator is approximately 6 db. this function is valid when the lthr pin is in the normal mode. because data is shifted into this pin in synchronization with the rising edge of the sync signal, hold the data at the pin for 250 s or longer. this pin setting is logically ored with the cr4-b1 bit of the control register. refer to the section ?relationship between pins and control registers?. aatt aatt aatt aatt this is the att atlenuation selection pin to prevent howling by means of attenuators (attsa, attra) provided in the rina inputs and souta outputs of the echo canceler. a logic ?0? selects 6 db and a logic ?1? selects 12 db. if input is only to rina, the attsa for souta is activated. if input is only to sina, or if there is input to both sina and rina, the attra for rina input is activated. this function is valid when the athr pin is in the normal mode. because data is shifted into this pin in synchronization with the rising edge of the sync signal, hold the data at the pin for 250 s or longer. this pin setting is logically ored with the cr5-b1 bit of the control register. refer to the section ?relationship between pins and control registers?.
fedl7731-02-04 1 semiconductor MSM7731-02 10/53 lgc lgc lgc lgc / agc agc agc agc this pin turns on or off the gain control function to control the input level and prevent howling by means of gain controls (gainl/a) provided in the rinl/a inputs of the echo canceler. the gain controller adjusts the rinl/a input level when it is ?10 dbm0 or above, and it has the control range of 0 to ?8.5 db. a logic ?0? turns the function on and a logic ?1? turns the function off. this function is valid when the lthr/athr pin is in the mormal mode. because data is shifted into this pin in synchronization with the rising edge of the sync signal, hold the data at the pin for 250 s or longer. this pin is ored with the cr4-b0 and cr5-b0 bits of the control register. refer to the section ?relationship between pins and control registers?. notes: lxx/axx : in the above, lxx refers to line echo canceler control pins and axx to acoustic echo canceler control pins. xxl/xxa : in the above pin descriptions, xxl refers to line echo canceler functions and xxa to acoustic echo canceler functions. glpadthr glpadthr glpadthr glpadthr this is the mode control pin for the attenuators (lpadl/a) provided in the sinl/a inputs and the amplifiers (gpadl/a) provided in the soutl/a outputs of the echo canceler. a logic ?0? selects the ?through mode? and a logic ?1? selects the normal mode (pad operation). the levels are set by the cr10 register. settings of 18, 12, 6 and 0 db are possible. the default setting is 12 db. if the echo return loss (value of returned echo) is amplified, set the lpad level such that echo return loss will be attenuated. it is recommended to set the gpad level to the positive level equal to the lpad level. if the pin setting is changed, the coefficient reset must be activated by either the rst pin or the rst bit (cr0-b6). because data is shifted into this pin in synchronization with the rising edge of the sync signal, hold the data at the pin for 250 s or longer. this pin is ored with the cr1-b2 bit of the control register. refer to the section ?relationship between pins and control registers?. rst rst rst rst this input pin resets coefficients of the echo canceler and noise canceler. a logic ?0? causes the reset state to be entered. at this time, the filter coefficients for the echo canceler and noise canceler are reset. control register contents are preserved. while reset is being processed, there is not sound. during normal operation, set this pin to a logic ?1?. use this pin in cases where the echo path changes (due to line switching during a telephone conversation, etc.), or when resuming telephone communication. because data is shifted into this pin in synchronization with the rising edge of the sync signal, hold the data at the pin for 250 s or longer. this pin is ored (negative logic) with the cr0-b6 bit of the control register. refer to the section ?relationship between pins and control registers?.
fedl7731-02-04 1 semiconductor MSM7731-02 11/53 ncsel1, ncsel2 these are the noise attenuation selection pins. in the ?through mode? the noise canceler is halted and data is directly output. in the ?normal mode? the noise canceler operates normally. since the noise attenuation in the normal mode is selected after the initial mode has been released, the change of the noise attenuation during normal operation is invalid. if the noise attenuation is changed, reset must be activated by the rdn / rst pin or the pdn/rst bit (cr0-b7). changing to the through mode during normal operation and returning to the normal mode are possible. the ncsel1 pin is ored with the cr1-b0 bit of the control register and the ncsel2 pin is ored with the cr12-b2 bit of the control register. refer to the section ?relationship between pins and control registers?. note: since there is a trade-off between noise attenuation and sound quality after canceling the noise, select the noise attenuation appropriate to the sound quality. ncsel2 ncsel1 nc mode attenuation (db) quality 0 0 normal mode 17 better 1 1 normal mode 13.5 1 0 normal mode 8 best 0 1 through mode ? ? ncpad1, ncpad2 these are the noise canceler i/o gain adjusting pins. the gain adjustment is valid for tone control after canceling the noise. the bigger the input level of the noise canceler is, the better the sound quality is. the ncpad1 pin is ored with the cr4-b2 bit of the control register and the ncpad2 pin is ored with the cr5-b2 bit of the control register. refer to the section ?relationship between pins and control registers?. ncpad2 ncpad1 gpadnc (db) lpadnc (db) 0000 016?6 1 0 12 ?12 1 1 18 ?18 den den den den , exck, din, dout this is the serial port for the microcontroller interface. 13 bytes of control registers are provided in this ic device. there pins are used to write and read data from an external microcontroller. the den pin is an enable signal input pin, the exck pin is a clock signal input pin for data shifting, the din pin is an address and data input pin, the dout pin is a data output pin. if the mirrocontroller interface is not used, set the den pin to a logic ?1? and the exck and din pins to a logic ?0?. in addition, use the mcusel pin to specify the ?unused? setting of the microcontroller interface. figure 4 shows the input timing. mcusel this pin selects whether the microcontroller interface is used or unused. a logic ?0? specifies that the microcontroller interface is used and a logic ?1? specifies that it is not used. if the microcontroller interface is not used, this pin must be set to a logic ?1?. this pin is ored with the cr0-b1 bit of the control register. refer to the section ?relationship between pins and control registers?. ?
fedl7731-02-04 1 semiconductor MSM7731-02 12/53 figure 4 microcontroller interface i/o timing w a6a5a4a3a2a1a0 b7b6b5b4b3b2b1b0 12345678 910111213141516 den exck din dout (a) data write timing 1 (8-bit mcu) hi-z w a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 12345678910111213141516 (b) data write timing 2 (16-bit mcu) hi-z den exck din dout r a6a5a4a3a2a1a0 b6 b5 b4 b3 b2 b1 b0 b7 12345678 910111213141516 (c) data read timing 1 (8-bit mcu) hi-z hi-z den exck din dout (d) data read timing 2 (16-bit mcu) 123456789 10 11 12 13 14 15 16 r a6a5a4a3a2a1a0 b6 b5 b4 b3 b2 b1 b0 b7 hi-z hi-z den exck din dout
fedl7731-02-04 1 semiconductor MSM7731-02 13/53 rpad4, rpad3, rpad2, rpad1 these are the receive signal gain adjusting and mute setting pins. refer to table 1 for the settings. set these pins to a logic ?0? when controlling by the control register. because data is shifted into this pin in synchronization with the rising edge of the sync signal, hold the data at the pin for 250 s or longer. for further details, refer to the electrical characteristics. these pins are ored with the cr2-b3, b2, b1 and b0 bits of the control register. refer to the section ?relationship between pins and control registers?. tpad4, tpad3, tpad2, tpad1 these are the transmit signal gain adjusting and mute setting pins. refer to table 1 for the settings. set these pins to a logic ?0? when controlling by the control register. because data is shifted into this pin in synchronization with the rising edge of the sync signal, hold the data at the pin for 250 s or longer. for further details, refer to the electrical characteristics. these pins are ored with the cr3-b3, b2, b1 and b0 bits of the control register. refer to the section ?relationship between pins and control registers?. table 1 rpad/tpad setting rpad4 rpad3 rpad2 rpad1 tpad4 tpad3 tpad2 tpad1 level 0111 011121 db 0110 011018 db 0101 010115 db 0100 010012 db 0011 00119 db 0010 00106 db 0001 00013 db 0000 00000 db 1111 1111?3 db 1110 1110?6 db 1101 1101?9 db 1100 1100 ?12 db 1011 1011 ?15 db 1010 1010 ?18 db 1001 1001 ?21 db 1000 1000mute test1-4 test inputs. set these pins to a logic ?0?. test9 test output.
fedl7731-02-04 1 semiconductor MSM7731-02 14/53 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd ? ?0.3 to +5.0 v digital input voltage v in ? ?0.3 to v dd +0.3 v digital output voltage v out ? ?0.3 to v dd +0.3 v storage temperature t stg ? ?55 to +150 c recommended operating condition parameter symbol condition min. typ. max. unit power supply voltage v dd ? 2.7 ? 3.6 v operating temperature t a ? ?40 +25 +85 c sync, bclk input pins 0.5v dd mck/x1 input pin 0.65v dd input high voltage v ih other digital input pins 0.45v dd ?v dd v mck/x1 input pin 0.35v dd input low voltage v il other digital input pins 0? 0.16v dd v digital input rise time t ir all digital inputs ? ? 20 ns digital input fall time t if all digital inputs ? ? 20 ns master clock frequency f mck mck/x1 ?100 ppm +19.2 +100 ppm mhz master clock duty ratio d mck mck/x1 40 50 60 % bit clock frequency f bck bclk (during output) 64 ? 2048 khz bit clock duty ratio d ck bclk (during output) 40 50 60 % synchronous signal frequency f sync sync (during output) ?100 ppm 8 +100 ppm khz synchronous signal width t ws sync (during output) 1 bclk ? 100 ns t bs bclk to sync (during input) 100 ? ? ns transmit/receive sync signal setting time t sb sync to bclk (during input) 100 ? ? ns r dl dout, pcmo, pcmeo 1 ? ? k ? c dl1 dout, pcmo, pcmeo ? ? 50 pf digital output load c dl2 sync, bclk (during output) ? ? 20 pf bypass condenser for sg c sg sg to ag 10+0.1 ? ? f
fedl7731-02-04 1 semiconductor MSM7731-02 15/53 electrical characteristics dc characteristics (v dd = 2.7 to 3.6 v, ta = ?25 to +85c) parameter symbol condition min. typ. max. unit power supply current 1 i dd1 operating, no signal (v dd = 3.0 v) ?3550ma power supply current 2 i dd2 power down mode (v dd = 3.0 v, mck = 0 v) ?0.02 1 ma i ih v i = v dd ?? 2a input leakage current i il v i = 0 v ? ? 2 a high level digital output voltage v oh i oh = 0.4 ma (other than 2) 0.5v dd ?v dd v low level digital output voltage v ol i ol = 3.2 ma (other than 2) ?0 0.2 0.4 v digital output leakage current i o dout, pcmo, pcmeo ? ? 10 a input capacitance c in ??5?pf analog interface characteristics (v dd = 2.7 to 3.6 v, ta = ?25 to +85c) parameter symbol condition min. typ. max. unit r ina ain, apwi 10 ? ? m ? input resistance r inl lin, lpwi 10 ? ? m ? r la1 agsx, avfro 20 ? ? k ? r la2 aout 1.2 ? ? k ? r ll1 lgsx, lvfro 20 ? ? k ? output load resistance r ll2 lout 1.2 ? ? k ? c la1 agsx, avfro, aout ? ? 100 pf output load capacitance c ll1 lgsx, lvfro, lout ? ? 100 pf v oa1 agsx, avfro r l = 20 k ? ??1.3vpp v oa2 aout r l = 1.2 k ? ??2.6vpp v ol1 lgsx, lvfro r l = 20 k ? ??1.3vpp output voltage level (*1) v ol2 lout r l = 1.2 k ? ??2.6vpp v ofa1 avfro ?100 ? +100 mv v ofa2 aout ?20 ? +20 mv v ofl1 lvfro ?100 ? +100 mv offset voltage v ofl2 lout ?20 ? +20 mv sg output voltage v sg sg ? 1.4 ? v sg output impedance r sg sg ? 40 80 k ? note*1: 0.320 vrms = 0 dbm0, +3.14 dbm0 = 1.30 v pp
fedl7731-02-04 1 semiconductor MSM7731-02 16/53 digital interface characteristics (1/3) (v dd = 2.7 to 3.6 v, ta = ?25 to +85c) parameter symbol condition min. typ. max. unit pdn / rst pin 1 power-down/reset signal pulse width t rstw pdn/rst control bit 1.6 ??s power-down/reset start time t pdnd pdn / rst pin and pdn/rst control bit ? ? 50 ns power down/reset end time t pdnh pdn / rst pin and pdn/rst control bit ? ? 200+ ms power-down/reset internal setting time t pdns sync pin (input mode) 140 ? 180 s control pulse width t parw 250 ? ? s control start time t pard ? ? 250 s control end time t parh (*2) ? ? 250 s : crystal activation pdn/rst timing pdn/rst set timing control timing (*2) note*2: applies to the following pins/control bits: lineen , slpthr, ncthr, glpadthr , tpad6-1, rpad6-1, rst , athr, aatt , ahld, ahd , agc , lthr, latt , lhld, lhd , lgc pins, and control bits. power down initial mode hi-z t pdnd t pdnh t rstw pdn / rst pin pdn/rst control bi t internal operation pcmo, pcmeo sync (ext. clock) bclk (ext. clock) pdn/rst control bit ( internal write ) t pdns internal processing t pard t parh t parw pin/control bit internal operation
fedl7731-02-04 1 semiconductor MSM7731-02 17/53 digital interface characteristics (2/3) (v dd = 2.7 to 3.6 v, ta = ?25 to +85c) parameter symbol condition min. typ. max. unit c dl = 20 pf (output mode, pcm) ?64 ?khz bit clock frequency f bck c dl = 20 pf (output mode, linear) ? 128 ? khz bit clock duty ratio d ck c dl = 20 pf (output mode) 40 50 60 % sync signal frequency f sync c dl = 20 pf (output mode) ? 8 ? khz sync signal duty ratio d sync c dl = 20 pf (output mode) 40 50 60 % t bs bclk to sync (output mode) 100 ? ? ns transmit/receive sync signal setting time t sb sync to bclk (output mode) 100 ? ? ns input setup time t ds ? 100 ? ? ns input hold time t dh ? 100 ? ? ns t sdx r dl = 1 k ? , c dl = 50 pf ? ? 100 ns digital output delay time t xd1 r dl = 1 k ? , c dl = 50 pf ? ? 100 ns t xd2 r dl = 1 k ? , c dl = 50 pf ? ? 100 ns digital output hold time t xd3 r dl = 1 k ? , c dl = 50 pf ? ? 100 ns digital input timing (normal-sync) digital input timing (short-frame-sync) bclk sync pcmi pcmei 1 0 2345678910 msb lsb t bs t sb t ws t ds t dh bclk sync pcmi pcmei 1 0 2345678910 msb lsb t bs t sb t ws t ds t dh
fedl7731-02-04 1 semiconductor MSM7731-02 18/53 digital output timing (normal-sync) digital output timing (short-frame-sync) digital interface characteristics (3/3) (v dd = 2.7 to 3.6 v, ta = ?25 to +85c) parameter symbol condition min. typ. max. unit t m1 ?20??ns t m2 ?20??ns t m3 ?50??ns t m4 ? 100 ? ? ns t m5 ?50??ns t m6 ?50??ns t m7 r d = 1 k ? , c dl = 20 pf ? ? 30 ns t m8 r d = 1 k ? , c dl = 20 pf 0 ? ? ns t m9 ?50??ns t m10 r d = 1 k ? , c dl = 20 pf ? ? 30 ns mcu interface digital input/output setting time t m11 ? 100 ? ? ns exck clock frequency f exck ???10mhz bclk sync pcmo pcmeo 1 0 2345678910 msb lsb t bs t sb t ws t sdx t xd1 t xd2 hi-z hi-z t xd3 bclk sync pcmo pcmeo 1 0 2345678910 t bs t sb t ws msb lsb t xd2 hi-z hi-z t xd3 t xd1
fedl7731-02-04 1 semiconductor MSM7731-02 19/53 microcontroller interface i/o timing den exck din dout t m1 t m2 t m3 t m4 t m5 t m6 t m7 t m8 t m10 t m11 t m9 12345678910111213141516 w/ra6a5a4a3a2a1a0b7 b6b5b4 b3b2b1b0 b7 b6 b5 b4 b3 b2 b1 b0
fedl7731-02-04 1 semiconductor MSM7731-02 20/53 ac characteristic (line side codec/acoustic side codec) (v dd = 2.7 to 3.6 v, ta = ?40 to +85c) condition parameter symbol freq. (hz) level (dbm0) others min. typ. max. unit l oss t1 0 to 60 25 ? ? l oss t2 300 to 3000 ?0.15 ? +0.20 l oss t3 1020 reference l oss t4 3300 ?0.15 ? +0.80 l oss t5 3400 0 ? 0.80 transmit frequency response l oss t6 3968.75 0(*3) 13 ? ? db l oss r1 0 to 3000 ?0.15 ? +0.20 l oss r2 1020 reference l oss r3 3300 ?0.15 ? +0.80 l oss r4 3400 0 ? 0.80 receive frequency response l oss r5 3968.75 0(*3) 13 ? ? db sd t1 3 35 ? ? sd t2 0 35 ? ? sd t3 ?30 35 ? ? sd t4 ?40 28 ? ? transmit signal to distortion ratio sd t5 1020 ?45 (*3, *4) 23 ? ? db sd r1 3 35 ? ? sd r2 0 35 ? ? sd r3 ?30 35 ? ? sd r4 ?40 28 ? ? receive signal to distortion ratio sd r5 1020 ?45 (*3, *4) 23 ? ? db gt t1 3 ?0.2 ? +0.2 gt t2 ?10 reference gt t3 ?40 ?0.2 ? +0.2 gt t4 ?50 ?0.5 ? +0.5 transmit gain tracking gt t5 1020 ?55 (*3) ?1.2 ? +1.2 db gt r1 3 ?0.2 ? +0.2 gt r2 ?10 reference gt r3 ?40 ?0.2 ? +0.2 gt r4 ?50 ?0.5 ? +0.5 receive gain tracking gt r5 1020 ?55 (*3) ?1.2 ? +1.2 db n idlt ??(*3, *4)?? ?68 (?75.7) idle channel noise n idlr ??(*3, *4)?? ?72 (?79.7) dbm0p (dbmp) a vt a/lgsx (*3) 0.285 0.32 0.359 vrms absolute signal amplitude a vr 1020 0 a/lvfro (*3) 0.285 0.32 0.359 vrms p srrt 30 ? ? db power supply noise rejection ratio p srrr noise freq: 0 to 50 khz noise level: 50 mv pp (*3) 30 ? ? db note: *3. codec input/output gain = 1 *4. p-message weighted filter used 0.320 vrms = 0 dbm0 = ?7.7 dbm
fedl7731-02-04 1 semiconductor MSM7731-02 21/53 noise canceler characteristics (v dd = 2.7 to 3.6 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit noise attenuation n res white noise, voice band 13 17 ? db measurement system block diagram echo canceler characteristics (v dd = 2.7 to 3.6 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit acoustic line side (when codec or 16-bit linear data interface is used) 35 echo attenuation e res line side (-law pcm used) ? 30 ?db t acoud single mode ? ? 59 ms t acoud dual mode (acoustic side) ? ? 59?t lined ms cancelable echo delay time t lined dual mode (line side) ? ? 27 ms measurement system block diagram l.p.f. 5 khz analog ain nc lout analog level meter MSM7731-02 power supply voltage 3 v codec input gain = 1 codec output gain = 1 white noise generator l.p.f. 5 khz analog rin rout analog delay MSM7731-02 power supply voltage 3 v codec input gain = 1 codec output gain = 1 white noise generator line or acoustic ec sout sin analog analog level meter att e.r.l (echo return loss) echo delay time t d
fedl7731-02-04 1 semiconductor MSM7731-02 22/53 rin input level vs. echo attenuation (measuring conditions) rin signal : 5 khz band white noise e.r.l : ?6 db delay time : 4 ms att, gc : off noise floor : ?60 dbm (p-message filter unused) e.r.l level vs. echo attenuation (with glpad) (measuring condition) rin signal : 5 khz band white noise rin input level : ?20 dbm (with glpad = 0 db) : ?26 dbm (with glpad = 6 db) : ?32 dbm (with glpad = 12 db) : ?38 dbm (with glpad = 18 db) delay time : 4 ms att, gc : off noise floor : ?60 dbm (p-message filter unused) e.r.l vs. echo attenuation (with glpad) 45 echo attenuation [db] 40 35 30 25 20 15 10 5 0 e.r.l [db] -40 0 5 10 15 20 25 glpad= 0db glpad= 6db glpad= 12db glpad= 18db -35 -30 -25 -20 -15 -10 -5 rin input level vs. echo attenuation 0 5 10 15 20 25 30 35 40 45 -50 rin input level [dbm] echo attenuation [db] -45 -40 -35 -30 -25 -20 -15 -10
fedl7731-02-04 1 semiconductor MSM7731-02 23/53 echo delay time vs. echo attenuation (dual echo canceler mode/acoustic side) (measuring condition) rin signal : 5 khz band white noise rin input level : ?16 dbm e.r.l : ?6 db att, gc : off noise floor : ?60 dbm (p-message filter unused) echo delay time vs. echo attenuation (dual echo canceler mode/line side) (measuring condition) rin signal : 5 khz band white noise rin input level : ?16 dbm e.r.l : ?6 db att, gc : off noise floor : ?60 dbm (p-message filter unused) echo delay time vs. echo attenuation dual echo canceler mode (acoustic side) 0 5 10 15 20 25 30 35 40 45 5 10 15202530 35404550 5560 echo delay time [ms] echo attenuation [db] echo delay time vs. echo attenuation 5 10 15202530 35404550 5560 echo delay time [ms] 0 5 10 15 20 25 30 35 40 45 echo attenuation [db] dual echo canceler mode (line side)
fedl7731-02-04 1 semiconductor MSM7731-02 24/53 echo delay time vs. echo attenuation (single echo canceler mode) (measuring condition) rin signal : 5 khz band white noise rin input level : ?16 dbm e.r.l : ?6 db att, gc : off noise floor : ?60 dbm (p-message filter unused) slope filter frequency characteristic (with codec filter frequency characteristic) (measuring condition) rin input level : ?16 dbm noise floor : ?60 dbm (p-message filter unused) echo delay time vs. echo attenuation single echo canceler mode 0 5 10 15 20 25 30 35 40 45 5 10 152025 3035 404550 5560 echo delay time [ms] echo attenuation [db] slope filter frequency characteristic 0 10 -10 -20 -30 -40 -50 -60 1001 501 1 1501 2001 2501 3001 3501 frequency [ms] gain [db]
fedl7731-02-04 1 semiconductor MSM7731-02 25/53 echo canceler characteristics data 1 (line echo, white noise) (measuring condition) rin signal : 5 khz band white noise rin input level : ?20 dbm e.r.l : 0 db att, gc : off noise floor : ?60 dbm (p-message filter unused) echo attenuation = 40 db echo canceler characteristics data 2 (line echo, voice) (measuring condition) rin signal : voice rin input level : about ?20 dbm e.r.l : 0 db att, gc : off noise floor : ?60 dbm (p-message filter unused) echo attenuation = 34 db echo canceler characteristics data 3 (acoustic echo, voice) (measuring condition) rin signal : voice rin input level : about ?20 dbm speaker output level : 80 db (a) (at 1 m) distance from microphone and speaker : 5 cm gc : off att, noise canceler : off noise floor : ?60 dbm (p-message filter unused) echo attenuation = 34 db measurement system block diagram (acoustic echo) 3 v + r9 22 k mic c10 1 agsx ain avfro apwi aout ag sp r13 22 k r14 22 k r15 1.2 k rv4 10 k rv1 0.734 k r8 2.2 k c9 10 r7 100 j1 mic c13 0.1 r16 10 k 1 2 3 4 8 7 6 5 r17 470 k c15 10 p ag 5 v j3 sp c14 0.1 m7731 ec sout sin rout rin u13lm4861
fedl7731-02-04 1 semiconductor MSM7731-02 26/53 functional description control registers table 2 control register map address contents a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr0 0 0 0 0 0 0 0 *pdn/rst *rst *# lineen # clken # pcmen # pcmeen ope *#mcusel ope *#ecsel r/w cr1 0 0 0 0 0 0 1 #dmwr ? ? ? ? * glpadthr *slpthr *#ncsel1 r/w cr2 0 0 0 0 0 1 0 ? ? rpad6 rpad5 *rpad4 *rpad3 *rpad2 *rpad1 r/w cr3 0 0 0 0 0 1 1 ? ? tpad6 tpad5 *tpad4 *tpad3 *tpad2 *tpad1 r/w cr4 0 0 0 0 1 0 0 *lthr ? lhld * lhd lclp *ncpad1 * latt * lgc r/w cr5 0 0 0 0 1 0 1 *athr ? ahld * ahd aclp *ncpad2 * aatt * agc r/w cr6 0 0 0 0 1 1 0 a15 a14 a13 a12 a11 a10 a9 a8 r/w cr70000111a7a6a5a4a3a2a1a0r/w cr8 0 0 0 1 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 r/w cr90001001 d7 d6 d5 d4 d3 d2 d1 d0 r/w cr10 0 0 0 1 0 1 0 gpada2 gpada1 lpada2 lpada1 gpadl2 gpadl1 lpadl2 lpadl1 r/w cr11 0 0 0 1 0 1 1 ready ? ? ? ? ? *#pcmsel #sypdn r/w cr12 0 0 0 1 1 0 0 ? ? ? ? ? *#ncsel2 ? ? r/w note * : shared control bits with port (pin) ? : reserved bits. do not change the initial value (?0?). # : control bit that can be changed only in the initial mode. reg name
fedl7731-02-04 1 semiconductor MSM7731-02 27/53 (1) cr0 (basic operating mode setting) b7 b6 b5 b4 b3 b2 b1 b0 cr0 pdn/rst rst lineen clken pcmen pmceen ope mcusel ope ecsel initial value (*5) 00000000 note*5: initial values are the values set when reset is activated by the pdn / rst pin. (initial values are also set in the same manner, except for cr0-b7, when reset by the pdn/rst bit of b7.) b7 power-down and reset 0: power-on 1: power-down reset during power-down reset, this device enters the power-down state. at this time all control register bits, internal variables, and the coefficients for the echo canceler and noise canceler are reset. after power- down reset is released, this device enters the initial mode. this bit is internally ored with the inverted pdn / rst signal. refer to the section ?relationship between pins and control registers?. b6 reset control 0: normal operation 1: reset at reset, the coefficients for the echo canceler and noise canceler and noise canceler are reset. control register contents preserved. while reset is being processed, there is no sound. use this bit in cases where the echo path changes (due to line switching during a telephone conversation, etc.), or when resuming telephone communication. because data is read by this bit in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the inverted rst signal. refer to the section ?relationship between pins and control registers?. b5 line codec power-down control 0: normal operation 1: power-down during power-down, the line codec is in the power-down state, the line codec output pin is at high impedance and line codec input pin is internally processed as an idle pattern input. this bit is internally ored with the lineen pin. when the line codec is not used, this control results in low consumption of electrical power. this bit can only be set to ?0? or ?1? during power-down reset and initial mode. refer to the section ?relationship between pins and control registers?. b4 sync, bclk output control 0: on 1: off when off, the sync and bclk output pins are in the high impedance state. this control is valid when the clksel pin is at a logic ?0? and has selected the internal clock mode. when the sync and bclk clocks are not used externally, this control results in low consumption of electrical power. this bit can only be set to "0" or "1" during power-down reset and the initial mode. b3 pcmi/o control 0:on 1: off when off, the pcmo output pin is in the high impedance state and the pcmi input pin is internally processed as an idle pattern input. when the line digital interface is not used, this control results in low consumption of electrical power. this bit can only be set to "0" or "1" during power-down reset and the initial mode. b2 pcmei/o control 0:on 1: off when off, the pcmeo output pin is in the high impedance state and the pcmei input pin is internally processed as an idle pattern input. when the line digital interface is not used, this control results in low consumption of electrical power. this bit can only be set to "0" or "1" during power-down reset and the initial mode.
fedl7731-02-04 1 semiconductor MSM7731-02 28/53 b1, b0 operation mode selection (0, 0): initial mode approximately 200 ms after power-down reset is released, the initial mode is entered. only in this mode can the contents of the internal default value store memory be modified and cr0-b5 to cr0-b0, cr1-b7, cr1-b0, cr11-b1, cr11-b0, and cr12-b2 be set. in this mode, digital signal output pins are at high impedance, digital communication input pins are internally processed as idle pattern inputs, and neither the echo canceler nor the noise canceler operates. this mode is skipped when the mcusel pin is a logic ?1?. this mode is released by setting the modes shown below. refer to the flow chart of figure 5. (1, 0): dual echo canceler mode the acoustic echo canceler, line echo canceler and other functions can be operated by control from the control registers. refer to figure 6. the initial setting for cancelable echo delay time is as follows: acoustic delay time = 44 ms line delay time = 15 ms (1, 1): single echo canceler mode the acoustic echo canceler and other functions can be operated by control from the control registers. control of the line echo canceler is unnecessary in this mode .refer to figure 7. the initial setting for cancelable echo delay time is as follows: acoustic delay time = 59 ms (other): reserved bit (cannot be used) note: the mcusel pin is internally ored with b1, and the ecsel pin is internally ored with b0. to return to the initial mode after it has been released, activate power-down reset. automatic setting acoustic codec acoustic echo canceler line codec noise canceler slope filter figure 7 single echo canceler mode acoustic codec acoustic echo canceler line codec noise canceler slope filter line echo canceler figure 6 dual echo canceler mode automatic setting pdn/rst pdn/rst release set control re g ister ready(cr11-b7) = 1 modify default store memory cr0-b1=1 start normal operation power-down state yes no wait for 200 ms ? control registers are reset. ? internal variables are reset. initial mode figure 5 initial mode flowchart ready(cr11-b7) = 0
fedl7731-02-04 1 semiconductor MSM7731-02 29/53 (2) cr1 b7 b6 b5 b4 b3 b2 b1 b0 cr1 dmwr ? ? ? ? glpadthr slpthr ncsel1 initial value 0 0 0 0 0 0 0 0 b7 internal data memory write control 0: write inhibited 1: write in internal data memory, the data set in cr8 (d15 to d8) and cr9 (d7 to d0) is written to the memory address set in cr6 (a15 to a8) and cr7 (a7 to a0). writing is possible only during the initial mode. for further details, refer to the internal data memory access method. b6, b5, b4, b3 reserved bits. modification of initial values is inhibited. b2 echo canceler i/o pad control 0: ?through mode? 1: normal mode this bit controls the attenuators (lpadl/a) provided in the sinl/a inputs and the amplifiers (gpadl/a) provided in the soutl/a outputs of the echo canceler. levels are set by the cr10 register, and 18, 12, 6 and 0 db can be set. the default value is 12 db. use this bit when the echo return loss (value of returned echo) is amplified. if the pin setting is changed, the coefficient reset must be activated by either the rst pin or the rst bit (cr0-b6). because data is read by this bit in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the glpadthr pin. b1 slope filter control 0: normal mode (slope filter operation) 1: ?through mode? this bit controls operation of the transmit slope filter. in the ?through mode?, the filter is halted and data is output directly. the slope filter decreases noises of low frequencies and improves the speech quality. refer to the frequency characteristics of slope filter. because data is read by this bit in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the slpthr pin. b0 noise attenuation selection control 0: normal mode 1: ?through mode? this bit selects the noise attenuation of the noise canceler. in the ?through mode?, the noise canceler is halted and data is output directly. in the ?normal mode? the noise canceler operates normally. since the noise attenuation in the normal mode is selected after the initial mode has been released, the change of the noise attenuation during normal operation is invalid. if the noise attenuation is changed, reset must be activated by the rdn / rst pin or the pdn/rst bit (cr0-b7). changing to the through mode during normal operation and returning to the normal mode are possible. this bit is internally ored with ncsel1 pin. (refer to the ncsel2 pin of cr12-b2.) note: since there is a trade-off between noise attenuation and sound quality after canceling the noise, select the noise attenuation appropriate to the sound quality. ncsel2 ncsel1 nc mode attenuation (db) quality 0 0 normal mode 17 better 1 1 normal mode 13.5 1 0 normal mode 8 best 0 1 through mode ? ? ?
fedl7731-02-04 1 semiconductor MSM7731-02 30/53 (3) cr2 (receive side level control) b7 b6 b5 b4 b3 b2 b1 b0 cr2 ? ? rpad6 rpad5 rpad4 rpad3 rpad2 rpad1 initial value 0 0 0 0 0 0 0 0 b7, b6 reserved bit. modification of initial values is inhibited. b5, b4, b3, b2, b1,b0 receive side level setting (rpad) these bits adjust the receive signal gain and set the mute level. notice that only the mute level setting differs from pin control. because data is read by these bits in synchronization with the rising edge of the sync signal, hold the data in these bits for 250 s or longer. when using this register, set the tpad, 3, 2, 1 pins to a logic ?0?. (0, 0, 1, 0, 1, 0): 30 db (0, 0, 1, 0, 0, 1): 27 db (0, 0, 1, 0, 0, 0): 24 db (0, 0, 0, 1, 1, 1): 21 db (0, 0, 0, 1, 1, 0): 18 db (0, 0, 0, 1, 0, 1): 15 db (0, 0, 0, 1, 0, 0): 12 db (0, 0, 0, 0, 1, 1): 9 db (0, 0, 0, 0, 1, 0): 6 db (0, 0, 0, 0, 0, 1): 3 db (0, 0, 0, 0, 0, 0): 0 db (1, 1, 1, 1, 1, 1): ?3 db (1, 1, 1, 1, 1, 0): ?6 db (1, 1, 1, 1, 0, 1): ?9 db (1, 1, 1, 1, 0, 0): ?12 db (1, 1, 1, 0, 1, 1): ?15 db (1, 1, 1, 0, 1, 0): ?18 db (1, 1, 1, 0, 0, 1): ?21 db (1, 1, 1, 0, 0, 0): ?24 db (1, 1, 0, 1, 1, 1): ?27 db (1, 1, 0, 1, 1, 0): ?30 db (1, 1, 0, 1, 0, 1): ?33 db (1, 1, 0, 1, 0, 0): ?36 db (1, 1, 0, 0, 1, 1): ?39 db (1, 1, 0, 0, 1, 0): ?42 db (1, 1, 0, 0, 0, 1): ?45 db (1, 1, 0, 0, 0, 0): ?48 db (1, 0, 1, 1, 1, 1): ?51 db (1, 0, 1, 1, 1, 0): ?54 db (1, 0, 1, 1, 0, 1): ?57 db (1, 0, 1, 1, 0, 0): ?60 db (1, 0, 1, 0, 1, 1): mute
fedl7731-02-04 1 semiconductor MSM7731-02 31/53 (4) cr3 (transmit gain adjustment) b7 b6 b5 b4 b3 b2 b1 b0 cr3 ? ? tpad6 tpad5 tpad4 tpad3 tpad2 tpad1 initial value 0 0 0 0 0 0 0 0 b7, b6 reserved bits. modification of initial values is inhibited. b5, b4, b3, b2, b1, b0 transmit side level setting (tpad) these bits adjust the transmit signal gain and set the mute level. notice that only the mute level setting differs from pin control. because data is read by these bits in synchronization with the rising edge of the sync signal, hold the data in these bits for 250 s or longer. when using this register, set the tpad4, 3, 2, 1 pins to a logic ?0?. (0, 0, 1, 0, 1, 0): 30 db (0, 0, 1, 0, 0, 1): 27 db (0, 0, 1, 0, 0, 0): 24 db (0, 0, 0, 1, 1, 1): 21 db (0, 0, 0, 1, 1, 0): 18 db (0, 0, 0, 1, 0, 1): 15 db (0, 0, 0, 1, 0, 0): 12 db (0, 0, 0, 0, 1, 1): 9 db (0, 0, 0, 0, 1, 0): 6 db (0, 0, 0, 0, 0, 1): 3 db (0, 0, 0, 0, 0, 0): 0 db (1, 1, 1, 1, 1, 1): ?3 db (1, 1, 1, 1, 1, 0): ?6 db (1, 1, 1, 1, 0, 1): ?9 db (1, 1, 1, 1, 0, 0): ?12 db (1, 1, 1, 0, 1, 1): ?15 db (1, 1, 1, 0, 1, 0): ?18 db (1, 1, 1, 0, 0, 1): ?21 db (1, 1, 1, 0, 0, 0): ?24 db (1, 1, 0, 1, 1, 1): ?27 db (1, 1, 0, 1, 1, 0): ?30 db (1, 1, 0, 1, 0, 1): ?33 db (1, 1, 0, 1, 0, 0): ?36 db (1, 1, 0, 0, 1, 1): ?39 db (1, 1, 0, 0, 1, 0): ?42 db (1, 1, 0, 0, 0, 1): ?45 db (1, 1, 0, 0, 0, 0): ?48 db (1, 0, 1, 1, 1, 1): ?51 db (1, 0, 1, 1, 1, 0): ?54 db (1, 0, 1, 1, 0, 1): ?57 db (1, 0, 1, 1, 0, 0): ?60 db (1, 0, 1, 0, 1, 1): mute
fedl7731-02-04 1 semiconductor MSM7731-02 32/53 (5) cr4 (line echo canceler setting) b7 b6 b5 b4 b3 b2 b1 b0 cr4 lthr ? lhld lhd lclp ncpad1 latt lgc initial value 0 0 0 0 0 0 0 0 b7 ?through mode? control 1: ?through mode? 0: normal mode (echo canceler operation) this is the ?through mode? control bit for the line echo canceler. in the ?through mode?, rinl and sinl data is output directly to routl and soutl respectively while each echo coefficient is maintained . in the through mode, the functions of lhd , lhld, latt and lgc are invalid. because data is read by this bit in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the lthr pin. b6 reserved bit. modification of initial values is inhibited. b5 coefficient update control 1: fixed coefficients 0: updated coefficients this bit selects whether the adaptive fir filter (afr) coefficients for the line echo canceler will be updated. this unction is valid when the athr pin is in the normal mode. because data is read into this bit by synchronization with the rising edge of the sync signal, hold the data at the bit for 250 s or longer. b4 howling detector control 1: off 0: on this bit controls the function to detect and cancel the howling that occurs in an acoustic system such as a handsfree communication system. this function is valid when the lthr pin is in the normal mode. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the lhd pin. b3 center clip control 1: on 0: off when the soutl output of the line echo canceler is ?57 dbm0 or less, the center clip function forcibly sets it to the minimum positive value. this function is valid when the lthr pin is in the normal mode. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. b2 ncpad control this bit adjusts the noise canceler i/o gain. the gain adjustment is valid for tone control after canceling the noise. the bigger the input level of the noise canceler is, the better the sound quality is. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the ncpad1 pin. (refer to the ncpad2 pin of cr5-b2.) ncpad2 ncpad1 gpadnc (db) lpadnc (db) 0000 016?6 1 0 12 ?12 1 1 18 ?18
fedl7731-02-04 1 semiconductor MSM7731-02 33/53 b1 attenuator control 1: att off 0: att on this bit turns on or off the att function to prevent howling by means of attenuators (attsl, attrl) provided in the rinl input and soutl output of the line echo canceler. if input is only to rinl, the att for soutl (attsl) is activated. if input is only to sinl, or if there is input to both sinl and rinl, the att for rinl input (attrl) is activated. the att value of each attenuator is approximately 6 db. this function is valid when the lthr pin is in the normal mode. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the latt pin. b0 gain controller 1: gc off 0: gc on this bit turns on or off the gain control function to control the rinl input level and prevent howling by means of a gain controller (gainl) provided in the rinl input of the line echo canceler. the gain controller adjusts the rin input level when it is ?10 dbm0 or above, and it has the control range of 0 to ?8.5 db. this function is valid when the lthr pin is in the normal mode. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the lgc pin.
fedl7731-02-04 1 semiconductor MSM7731-02 34/53 (6) cr5 (acoustic echo canceler setting) b7 b6 b5 b4 b3 b2 b1 b0 cr5 athr ? ahld ahd aclp ncpad2 aatt agc initial value 0 0 0 0 0 0 0 0 b7 ?through mode?control 1: ?through mode? 0: normal mode (echo canceler operation) this is the ?through mode? control bit for the acoustic echo canceler. in the ?through mode?, rina and sina data is output directly to routa and souta respectively while each echo coefficient is maintained. in the through mode, the functions of ahd , ahld, aatt and agc are invalid. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the athr pin. b6 reserved bit. modification of initial values is inhibited. b5 coefficient update control 1: fixed coefficients 0: updated coefficients this bit selects whether the adaptive fir filter (afr) coefficients for the acoustic echo canceler will be updated. this function is valid when the athr pin is in the normal mode. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. b4 howling detector control 1: off 0: on this bit controls the function to detect and cancel the howling that occurs in an acoustic system such as a handsfree communication system. this function is valid when the athr pin is in the normal mode. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the ahd pin. b3 center clip control 1: on 0: off when the souta output of the acoustic echo canceler is ?57 dbm0 or less, the center clip function forcibly sets it to the minimum positive value. this function is valid when the athr pin is in the normal mode. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. b2 ncpad control this bit adjusts the noise canceler i/o gain. the gain adjustment is valid for tone control after canceling the noise. the bigger the input level of the noise canceler is, the better the sound quality is. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the ncpad2 pin. (refer to the ncpad1 pin of cr4-b2.) ncpad2 ncpad1 gpadnc (db) lpadnc (db) 0000 016?6 1 0 12 ?12 1 1 18 ?18
fedl7731-02-04 1 semiconductor MSM7731-02 35/53 b1 attenuator control 1: att 12 db 0: att 6 db this bit selects the attenuation of the att function to prevent howling by means of attenuators (attsa, attra) provided in the rina input and souta output of the acoustic echo canceler. if input is only to rina, the att for souta (attsa) is activated. if input is only to sina, or if there is input to both sina and rina, the att for rina input (attra) is activated. the att value of each attenuator is approximately 6 db or 12 db. this function is valid when the athr pin is in the normal mode. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the aatt pin. b0 gain controller control 1: gc off 0: gc on this bit turns on or off the gain control function to control the rina input level and prevent howling by means of a gain controller (gaina) provided in the rina input of the acoustic echo canceler. the gain controller adjusts the rin input level when it is ?10 dbm0 or above, and it has the control range of 0 to ?8.5 db. this function is valid when the athr pin is in the normal mode. because this bit is read in synchronization with the rising edge of the sync signal, hold the data in the bit for 250 s or longer. this bit is internally ored with the agc pin.
fedl7731-02-04 1 semiconductor MSM7731-02 36/53 (7) cr6 (internal data memory write register) b7 b6 b5 b4 b3 b2 b1 b0 cr6 a15 a14 a13 a12 a11 a10 a9 a8 initial value 0 0 0 0 0 0 0 0 b7 to b0 memory upper address control this register sets the upper address of memory. for the writing method, refer to the method of internal data memory access section. (8) cr7 (internal data memory write register) b7 b6 b5 b4 b3 b2 b1 b0 cr7 a7 a6 a5 a4 a3 a2 a1 a0 initial value 0 0 0 0 0 0 0 0 b7 to b0 memory lower address control this register sets the lower address of memory. for the writing method, refer to the method of internal data memory access section. (9) cr8 (internal data memory write register) b7 b6 b5 b4 b3 b2 b1 b0 cr8 d15 d14 d13 d12 d11 d10 d9 d8 initial value 0 0 0 0 0 0 0 0 b7 to b0 memory upper data control this register sets the memory?s upper data. for the writing method, refer to the method of internal data memory access section. (10) cr9 (internal data memory write register) b7 b6 b5 b4 b3 b2 b1 b0 cr9 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 b7 to b0 memory lower data control this register sets the memory?s lower data. for the writing method, refer to the method of internal data memory access section.
fedl7731-02-04 1 semiconductor MSM7731-02 37/53 (11) cr10 (echo canceler i/o level setting) b7 b6 b5 b4 b3 b2 b1 b0 cr10 gpada2 gpada1 lpada2 lpada1 gpadl2 gpadl1 lpadl2 lpadl1 initial value 0 0 0 0 0 0 0 0 b7, 6 acoustic output level control these bits control the pad level of the gain of the acoustic echo canceler?s souta output. pad is turned on or off by either the glpadthr pin or the glpadthr control register bit (cr1-b2). it is recommended to set the level to the positive level equal to lpada2 and lpada1. if the pin setting is changed, the coefficient reset must be activated by either the rst pin or the rst bit (cr0-b6). because these bits are read in synchronization with the rising edge of the sync signal, hold the data in these bits for 250 s or longer. (0, 1): + 18 db (0, 0): + 12 db (1, 1): + 6 db (1, 0): 0 db b5, 4 acoustic input level control these bits control the pad level of the loss of the acoustic echo canceler?s sina input. pad is turned on or off by either the glpadthr pin or the glpadthr control register bit (cr1-b2). set the level so that echo return loss (value of returned echo) will be attenuated. if the pin setting is changed, the coefficient reset must be activated by either the rst pin or the rst bit (cr0-b6). because these bits are read in synchronization with the rising edge of the sync signal, hold the data in these bits for 250 s or longer. (0, 1): ? 18 db (0, 0): ? 12 db (1, 1): ? 6 db (1, 0): 0 db b3, 2 line output level control these bits control the pad level of the loss of the line echo canceler?s soutl output. pad is turned on or off by either the glpadthr pin or the glpadthr control register bit (cr1-b2). it is recommended to set the level to the positive level equal to lpadl2 and lpadl1. if the pin setting is changed, the coefficient reset must be activated by either the rst pin or the rst bit (cr0-b6). because these bits are read in synchronization with the rising edge of the sync signal, hold the data in these bits for 250 s or longer. (0, 1): + 18 db (0, 0): + 12 db (1, 1): + 6 db (1, 0): 0 db b1, 0 line input level control these bits control the pad level of the loss of the line echo canceler?s sinl output. pad is turned on or off by either the glpadthr pin or the glpadthr control register bit (cr1-b2). set the level so that echo return loss (value of returned echo) will be attenuated. if the pin setting is changed, the coefficient reset must be activated by either the rst pin or the rst bit (cr0-b6). because these bits are read in synchronization with the rising edge of the sync signal, hold the data in these bits for 250 s or longer (0, 1): ? 18 db (0, 0): ? 12 db (1, 1): ? 6 db (1, 0): 0 db
fedl7731-02-04 1 semiconductor MSM7731-02 38/53 (12) cr11 (sync power-down control register) b7 b6 b5 b4 b3 b2 b1 b0 cr11ready?????pcmselsypdn initial value 0 0 0 0 0 0 0 0 b7 data write flag 1: write enabled 0: write disabled after power-down reset is released, this device enters the initial mode. this bit becomes ?1? only during the initial mode, enabling access to the internal data memory. checking this bit will detect whether writing by an external microcomputer is possible. b6 to b2 reserved bits. modification of initial values is inhibited. b1 pcm coding format control 1: -law pcm 0: 16-bit linear this is the coding format selection bit for digital data communication. a logic ?1? selects -law pcm and a logic ?0? selects 16-bit linear (2?s complement) coding format. the bclk signal determines the output clock frequency to be used when internal clock is selected. if the digital interface is not used, set this bit to logic ?0? to select 16-bit linear coding format. since this bit is ored with the pcmsel pin, set this bit to logic ?0? when controlling by the pin. if this bit setting is changed, reset must be activated by either the pdn / rst pin or the pdn/rst bit (cr0-b7). b0 sync-pdwn control 1: pdn/rst power-down 0: pdwn power-down this bit controls the function that automatically enters the power-down state when the sync signal is fixed to a logic ?1? or ?0?. this function is valid when the external clock mode has been selected by the clksel pin. two kinds of power-down modes can be selected. pdn/rst power-down mode if the sync signal is fixed at 8 khz or longer, this device automatically writes a logic 1 to the control register pdn/rst bit (cr0-b7) and enters the power-down reset state. to return to the normal operation, reset must be activated by either the pdn / rst pin or the pdn/rst bit (cr0-7). the state after returning to the normal operation is the same as that reset after power-on. pdwn power-down mode if the sync signal is fixed at 8 khz or longer, this device automatically enters the power-down state. during the power-down, the analog output is ?0? output (mute) and the sg output holds about 1.4 v. to return to the normal operation, detect the sync signal rise. in the state after returning to the normal operation, internal variables and coefficients of the echo canceler and noise canceler are reset. each bit of the control register is held and operates normally after about 200 ms. pdn/rst power-down pdwn power-down sypdn (cr11-b0) 1 0 internal process pdn/rst (cr0-b7) = 1 mute control power-down removal method pdn/rst pin or bit sync rising edge after removing power-down ?reset each bit of cr. internal coefficient. echo canceler coefficient. noise canceler coefficient. ?reset internal coefficient. echo canceler coefficient. noise canceler coefficient. ?hold each bit of cr. operating current typ. 0.02 ma tbd
fedl7731-02-04 1 semiconductor MSM7731-02 39/53 (13) cr12 (reserved register) b7 b6 b5 b4 b3 b2 b1 b0 cr12?????ncsel2?? initial value 0 0 0 0 0 0 0 0 b7 to b3 reserved bits. modification of initial values is inhibited. b2 noise attenuation selection control this bit selects the noise attenuation of the noise canceler. in the ?through mode?, the noise canceler is halted and data is output directly. in the ?normal mode? the noise canceler operates normally. since the noise attenuation in the normal mode is selected after the initial mode has been released, the change of the noise attenuation during normal operation is invalid. if the noise attenuation is changed, reset must be activated by the rdn / rst pin or the pdn/rst bit (cr0-b7). changing to the through mode during normal operation and returning to the normal mode are possible. this bit is internally ored with the ncsel2. (refer to the ncsel1 pin of cr1-b0.) note: since there is a trade-off between noise attenuation and sound quality after canceling the noise, select the noise attenuation appropriate to the sound quality. ncsel2 ncsel1 nc mode attenuation (db) quality 0 0 normal mode 17 better 1 1 normal mode 13.5 1 0 normal mode 8 best 0 1 through mode ? ? b1, b0 reserved bits. modification of initial value is inhibited. ?
fedl7731-02-04 1 semiconductor MSM7731-02 40/53 relationship between pins and control registers in this device, the same function is controlled by either a pin or a control register. for example, when a function is controlled by a pin, setting of the corresponding control register is important. table 3 shows the relationship between settings of pins when functions are controlled by control registers and setting of control registers when functions are controlled by pins. the setting value of a control register when a function is controlled by a pin is equal to its initial value when the device is reset by the pdn / rst pin or the pdn/rst bit (cr0-b7). table 3 relationship between pins and control registers function setting of pin when function is controlled by control register setting of control register when function is controlled by pin lineen logic ?0? 0 pdn / rst logic ?1? 0 pcmsel logic ?0? 0 ecsel logic ?0? 0 lthr/athr logic ?0? 0 lhd/ahd logic ?0? 0 latt/aatt logic ?0? 0 lgc/agc logic ?0? 0 glpadthr logic ?0? 0 slpthr logic ?0? 0 rst logic ?1? 0 mcusel logic ?0? 0 rpad4-1 logic ?0? 0 tpad4-1 logic ?0? 0 ncsel1, 2 logic ?0? 0 ncpad1, 2 logic ?0? 0
fedl7731-02-04 1 semiconductor MSM7731-02 41/53 control method by mcu start set cr6 set cr7 set cr8 set cr9 cr1 = 80h set other memory? start telecommunication cr1 = 00h no yes no yes power supply on set pdn/rst cancel pdn/rst cr11-b7 = 1 write internal memory? no yes yes no set cr1 to cr12 set cr0 cr11-b7 = 0 no yes internal memory write initial mode
fedl7731-02-04 1 semiconductor MSM7731-02 42/53 method of internal data memory access the default values such as the cancelable echo delay time, echo attenuation and noise attenuation can be changed during the initial mode (cr0-b1, cr0-b0 = ?00?). refer to the procedure below. 1. set the address of the default value store memory. (cr6, 7) 2. set the modified values (data). (cr8, 9) 3. set the write command. (cr1-b7 = "1") after the write operation is complete, the write command (cr1-b7) is cleared to ?0?. consecutive writes are possible. (example) in the case of changing the acoustic delay time in a single echo canceler mode to 30 ms. start cr6 = 00h cr7 = 9bh cr8 = 00h cr9 = f0h cr1 = 80h set other memory? end cr1 = 00h no yes no yes upper address setting lower address setting upper data setting lower data setting write control write complete confirmation address: 009bh, data: 00f0h
fedl7731-02-04 1 semiconductor MSM7731-02 43/53 echo canceler delay time cancelable echo delay time is as follows. (1) single echo canceler mode acoustic echo canceler default : 59 ms variable range : 0.5 to 59 ms (in 0.5 ms steps) line echo canceler operation is halted. (2) dual echo canceler mode (operation of acoustic and line echo cancelers) condition : acoustic delay time + line delay time 59 ms acoustic echo canceler default : 44 ms variable range : 0.5 to 58.5 ms (in 0.5 ms steps) line echo canceler default : 15 ms variable range : 0.5 to 27 ms (in 0.5 ms steps) memory addresses are shown below. (1) single echo canceler mode memory address of acoustic echo canceler delay time : 009bh (2) dual echo canceler mode (operation of acoustic and line echo cancelers) memory address of acoustic echo canceler delay time : 0099h memory address of line echo canceler delay time : 009ah the method for calculating delay time is shown below. delay time [s] 8000 = delay time data (hex) example of 30 ms: 0.03 8000 = 240 (dec) = 00f0 (hex) echo canceler mode echo canceler address default time default data changeable range acoustic side 0099h 44 ms 0160h 0.5 to 58.5 ms dual echo canceler line side 009ah 15 ms 0078h 0.5 to 27.0 ms acoustic side 009bh 59 ms 01d8h 0.5 to 59.0 ms single echo canceler line side???? notes : dual echo canceler mode condition acoustic echo canceler delay time + line echo canceler delay time 59 ms : setting delay time condition 0.5 ms steps (increment width)
fedl7731-02-04 1 semiconductor MSM7731-02 44/53 noise attenuation there is a trade-off between noise attenuation and sound quality. in other words, increasing the noise attenuation deteriorates sound quality, and decreasing the noise attenuation improves sound quality. the following combinations of noise attenuation levels can be selected with this device. select the noise attenuation appropriate to the sound quality. when selecting the following combinations by the method of internal data memory access, set the ncsel1/ncsel2 pin and bit as follows: ncsel1 pin and bit (cr1-b0) = 0 ncsel2 pin and bit (cr12-b2) = 0 data 1 data 2 noise attenuation [db] address 01c8h 01c2h voice quality 17 (default) 2000h 0005h better 14 3333h 0005h 13.5 3333h 0004h 12 4666h 0005h 11 4666h 0003h 10 5999h 0005h 9 6666h 0005h 8 5999h 0002h 8 2000h 0001h 8 3333h 0001h 7 4666h 0001h 7 5999h 0001h 6 6666h 0001h best attenuation of att function the attenuation (att values) of echo canceler att functions (attsl/attrl, attsa/attra) can be selected from the following combinations. when selecting the attenuation, take note of the following. 1. increasing the attenuation causes almost half duplex. 2. increasing the attenuation causes the sound of the beginning and ending of words to be cut. 3. increasing the attenuation remarkably changes the sound volume of background noise. (by turning on or off the atts/attr) when selecting the following combinations by the method of internal data memory access, set the aatt pin and bit as follows: aatt pin and bit (cr5-b1) = 0 data 1 data 2 data 3 data 4 data 5 att attenuation [db] address 0199h 019ch 019fh 01a2h 01a5h 6 (default) 4000h 4200h 4200h 4200h 4000h 12 2000h 4000h 2200h 2200h 2000h 18 1000h 4000h 2000h 1200h 1000h 24 0800h 4000h 2000h 1000h 0800h
fedl7731-02-04 1 semiconductor MSM7731-02 45/53 gain adjustment of external speaker amplifier the overflow (clipping) of speaker amplifier output occurred in the echo path between the echo canceler output (e.g. avfro) and the echo canceler input (e.g. agsx) decreases the echo attenuation remarkably. in other words, when an external speaker amplifier is used, do gain adjusting without overflow of speaker amplifier output. adjusting method 1 be careful of the following. 1. echo canceler output pin (avfro/lvfro) adjust the agsx/lgsx gain or rpad/tpad so as to set the output level to less than 1.3 v pp (typical level = -20 dbm0). 2. external speaker amplifier output pin adjust the gain so as to set the output level to less than the maximum output amplitude. adjusting method 2 the speaker amplifier output can be adjusted appropriately by making the echo canceler input signal clipped intentionally when the speaker amplifier output is small. 1. external speaker amplifier gain the analog maximum output amplitude of the msm7731 and the maximum output amplitude of external speaker amplifier determine the speaker amplifier gain. (example) avfro maximum output amplitude = 1.3 v pp gain of apwi and aout = 1 maximum output amplitude of external speaker amplifier = 10 v pp external speaker amplifier gain = speaker amplifier maximum output amplitude/avfro maximum output amplitude = 10/1.3 = less than 7.6 2. speaker output adjustment adjust the volume with the echo canceler input (rpad). the following shows the circuit diagram. avfro apwi aout 20 k ? 20 k ? 10 k ? c codec echo canceler rpad ? + 68 k ? speaker amplifier speaker msm7731
fedl7731-02-04 1 semiconductor MSM7731-02 46/53 difference between msm7731-01 and MSM7731-02 function control method msm7731-01 MSM7731-02 mcu control variable by initial download 17 db or through selectable by ncthr bit variable by initial download 17 db, 13.5 db, 8 db or through selectable by ncsel1, 2 bits noise attenuation selection pin control 17 db or through selectable by ncthr pin 17 db, 13.5 db, 8 db or through selectable by ncsel1, 2 pins mcu control none 0 db, 6 db, 12 db or 18 db selectable by ncpad1, 2 bits noise canceler i/o gain adjustment function pin control none 0 db, 6 db, 12 db or 18 db selectable by ncpad1, 2 pins mcu control variable by initial download 0 db or 6 db selectable by aatt bit variable by initial download 6 db or 12 db selectable by aatt bit acoustic echo canceler attenuator function pin control 0 db or 6 db selectable by aatt pin 6 db or 12 db selectable by aatt pin mcu control on or off selectable by ahld, lhld bit on or off selectable by ahld, lhld bits line acoustic echo canceler coefficient update function pin control on or off selectable by ahld, lhld pin always updated (on) mcu control power down function (pdn/rst) on or off selectable by sypdn bit *1 power down function (pdn/rst) on or off selectable by sypdn bit *1 sync power-down pin control none always operated (on) *1 power down function (pdwn) note*1: refer to the description of ?(12) cr11 (sync-pdwn control register)? of this data sheet. 1. pins (msm7731-01) (MSM7731-02) ncthr ncsel1 test8 ncsel2 lhld ncpad1 ahld ncpad2 2. control registers (msm7731-01) (MSM7731-02) cr1-b0 ncthr ncsel1 cr12-b2 x ncsel2 cr4-b2 lhld ncpad1 cr5-b2 ahld ncpad2 cr4-b5 x lhld cr5-b5 x ahld
fedl7731-02-04 1 semiconductor MSM7731-02 47/53 3. functions (MSM7731-02) noise attenuation selection function added (17, 13.5, 8 db, thr-selectable) noise canceler i/o gain adjustment function added (0, 6, 12, 18 db-selectable) acoustic echo canceler coefficient update pin control disabled line echo canceler coefficient update pin control disabled accoustic echo canceler attenuator attenuation changed, off function deleted (6, 12 db selectable) sync power-down control changed (pdn/rst power-down, pdwn power-down)
fedl7731-02-04 1 semiconductor MSM7731-02 48/53 notes on use 1. use a stabilized power supply with a low level of noises (especially spike noises and pulse noises of high frequencies) in order to prevent this device from malfunction or degradation in characteristics. 2. place a good characteristic of bypass-capacitor for the power supply near the pins of this device in order to assure its electrical characteristics. 3. place a good characteristic of bypass-capacitor for the analog signal ground (sg pin) near the pins of this device in order to assure its electrical characteristics. 4. connect the agnd, dgnd1 and dgnd 2 to the system ground at a shortest distance and in a low impedance state. 5. use a separate power supply for an external speaker amplifier so as not to be disturbed by externally generated noises. 6. when an external speaker amplifier is used, do gain adjusting without overflow (saturation) of speaker amplifier output. the overflow of speaker amplifier output decreases the echo attenuation. 7. set the analog signal input level to less than 1.3 v pp to prevent overlow. otherwise, voice will be distorted. 8. set the echo return loss (erl) to be attenuated. if the echo return loss is to be amplified, the glpad function should be used. the erl refers to echo attenuation (loss) between the echo canceler output (routa/routl) and the echo canceler input (sina/sinl). refer to characteristics diagram for the erl vs. echo attenuation. 9. the input level should be ?10 to ?20 dbm0. refer to characteristics diagram for the erl vs. echo attenuation. 10. adjust the volume at the position of the echo canceler input (rina/rinl). when in dual echo canceler mode : adjust the volume with tpad and rpad. when in signal echo canceler mode : adjust the volume with tpad and rpad, or with the analog input (lin) that is set at less than 1.3 v pp . 11. when the echo path is changed (when resuming telephone communication), reset the device with the rst pin or the rst bit. 12. after turning on the power, be sure to reset the device with the pdn / rst pin or the pdn/rst bit. 13. in order to get the highest performance of this device, the following functions should be used. aatt / latt : on agc / lgc : on slpthr : normal mode (slope filter operation) ncthr : normal mode (noise canceler operation) rpad6-1 : adjusting the volume of receive signal tpad6-1 : adjusting the volume of transmit signal
fedl7731-02-04 1 semiconductor MSM7731-02 49/53 application circuit sp (8 w) MSM7731-02 mic spamp a-ina a-outa linear codec acoustic echo canceler noise canceler slope filter line echo canceler liner codec a-outl a-inl sin rout rin sout rpad tpad rin sout sin rout clock gen timing gen mcu i/f ec/nc/pad controller p/s & s/p pcmo pcmi pcmeo pcmei msm6679b voice recognition processor vocabulary memor y p dn / rst mck/xi x2 sync syncsel bclk clksel pmcsel d en exck din dout mcusel lthr ahd aff aff
fedl7731-02-04 1 semiconductor MSM7731-02 50/53 application circuit (1) in case of line analog interface and pin control (ncsel = 13.5 db, ncpad = 6 db, trad = 9 db) line reset 10 p f 10 pf 19.2 mhz 1 m ? 3 v(d) 20 k ? 20 k ? 20 k ? 20 k ? 1 f 3 v(d) 0.1f 0.1 f + 0.1 f 3 v(a) + 10 f 10 k ? 10 f 3 v(d) 3 v(d) 1 f 3 v(d) 1 k ? 20 k ? 20 k ? 20 k ? speaker amplifier + sp lvfro lpwi lout lgsx lin sync bclk pcmi pcmo pcmei pcmeo den exck din dout pdn / rst rst clksel syncsel test1 test2 test3 test4 test9 dvdd1 dvdd2 dgnd1 dgnd2 avdd agnd sg avfro apwi aout agsx ain ncsel1 ncsel2 ncpad1 ncpad2 athr ahd aatt agc lthr lhd latt lgc lineen pcmsel slpthr mcusel ecsel glpadthr tpad1 tpad2 tpad3 tpad4 rpad1 rpad2 rpad3 rpad4 MSM7731-02 mck/x1 x2 mic rotary switch portable telephone interface 10 f 10 f
fedl7731-02-04 1 semiconductor MSM7731-02 51/53 application circuit (2) in case of line digital interface and mcu control dout din bclk sync 3 v(d) 3 v(d) reset 0.1 f 0.1 f + 10 f 0.1 f 3 v(a) + 10 f 10 f 1 f 1 k ? 20 k ? 20 k ? 20 k ? speaker amplifier + sp lvfro lpwi lout lgsx lin sync bclk pcmi pcmo pcmei pcmeo den exck din dout pdn / rst rst clksel syncsel test1 test2 test3 test4 test9 dvdd1 dvdd2 dgnd1 dgnd2 avdd agnd sg avfro apwi aout agsx ain ncsel1 ncsel2 ncpad1 ncpad2 athr ahd aatt agc lthr lhd latt lgc lineen pcmsel slpthr mcusel ecsel glpadthr tpad1 tpad2 tpad3 tpad4 rpad1 rpad2 rpad3 rpad4 MSM7731-02 mck/x1 x2 mic 10 pf 10 pf 19.2 mhz 1 m ? controller
fedl7731-02-04 1 semiconductor MSM7731-02 52/53 package dimensions (unit : mm) qfp64-p-1414-0.80-bk mirror finish package material pin treatment solder plate thickness lead frame material package weight (g) epoxy resin 42 alloy solder plating 5 m or more 0.87 typ. notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code, and desired mounting conditions (reflow method, temperature and times).
fedl7731-02-04 1 semiconductor MSM7731-02 53/53 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2000 oki electric industry co., ltd.

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